- Describing hardware
ECE 111 was the first course where the code was the circuit. The opening exercise builds the same decoder, adder and mux three ways (gates, dataflow, behavioural) and all three must simulate identically. The module shelf below starts there.
- The library, in the order it was built
ALU and counters, a Johnson counter, a barrel shifter, a maximal-length LFSR with programmable taps, Gray-to-binary, a carry-lookahead adder, a divide-by-N clock, a convolutional encoder, and a UART. Each card on the shelf is a live model of that module with its RTL and testbench verdict beside it.
- The final: a Viterbi decoder
A rate-½, 8-state convolutional code and the decoder that undoes it. Each clock, eight add-compare-select units extend eight candidate paths through the trellis by one symbol and keep the cheaper of the two ways into every state; after 64 symbols the oldest bit on the best path is the decoded bit. Burst errors are corrected as long as the true path stays cheapest.
- Simulated for this page
The decoder RTL had been completed with AI coding tools and never simulated. Building this page ran it through Icarus Verilog for the first time: the encoder's empty case table was filled in, the best-state search and survivor update were rewritten as continuous assigns (Icarus re-triggered the original always_comb loops forever at t=0), and the waveforms and pass/fail table are from that run.
- What the burst sweep showed
Single hits and pairs on one bit (2.a.1–2.a.5) decode cleanly; four in a row on either bit every 32 symbols (2.a.6, 2.a.7) and pairs on both bits (2.a.8) do not. The sweep pins the limits: a burst of five consecutive bad symbols on one bit breaks the decoder, and with both bits wrong a burst of two is already too much: with constraint length 3 the trellis simply has too little memory to outvote a longer burst.